As memory capacity is becoming larger, a memory can have higher possibility of random defects, particle contaminations, or manufacturing inefficiencies such that the memory may not be useable. A conventional approach is to use spare cells to replace defective cells.
FIG. 1 shows a block diagram of a portion of a conventional memory chip 20 as an example of memory repairs. The memory chip 20 has a memory array 21 coupled to an X-decoder 23, which couples to the output of an X-address buffer 25. An external X-address goes through X-address buffer 25 and then the X-decoder 23, to select a row 28 in the memory array 21. But if the row 28 is defective, this row needs to be replaced by a good row. A redundant row 22, a redundant X-decoder 24, a defective X-addresses storage 26, and a match circuit 27 can be built to serve this purpose. The defective X-address storage 26 stores the X-addresses of the defective rows in non-volatile memories, once the defective rows are found and tested. When an external X-address accesses a row, the X-address is input to both the normal X-decoder 23 and the redundant X-decoder 24 through the X-address buffers 25. The X-address is also input to the match circuit 27 to check if the defective X-address storage 26 stores the same address. If there is not a match, the normal row 28 will be selected. Otherwise, if there is a match, the redundant row 22 will be selected. The same concept can be applied to replace a defected column or a cell. As an example of a 1 Mb×8 memory with 10 X-addresses, 10 Y-addresses, and 8 I/Os, the required storage to specify a defective row is 10 bits for X-address and one bit to indicate a valid address for a total of 11 bits. To repair a faulty column for any I/Os, the require bits are 10 Y-address, 1 valid bit, and 3 bits for I/Os, or 14 bits total. The valid bit, or enable bit, is to indicate a valid redundant address; otherwise, an address with all un-programmed bits would be treated as a defective address. One-Time Programmable (OTP), a memory that can be programmed only once, is sufficient for use as the defective-address storage 26. The data stored in the non-volatile storage 26 are typically loaded into latches or registers before being used for address comparisons.
Laser fuses have been used to store defective addresses as a prior art since 1980s. FIG. 2(a) shows a block diagram of a one bit laser fuse cell 13. The cell 13 has a laser fuse 14 coupled to a circuit 18 to detect if the fuse is blown to generate a digital output Q. The laser fuse can be a polysilicon, silicided polysilicon, or metal. To allow a laser beam penetrating through the thick interlayer dielectrics (i.e. SiO2), the numbers of metal layers need to be limited, special layout rules need to be followed, and special testers need to be purchased for programming. Moreover, the laser cell size (˜10-100 um2) is determined by a laser beam spot and alignment clearness that can not be scaled with the ever shrinking MOS devices easily. Furthermore, the memory repair can only be done in the wafer level before packaging (i.e. not field programmable). As a result, this solution can not keep up with the developments of CMOS technologies in the 21st century.
A programmable resistive device can be used to store defective addresses for memory repairs. A programmable resistive device is generally referred to a device's resistance state that may change after means of programming. Resistance states can also be determined by resistance values. For example, a resistive device can be a One-Time Programmable (OTP) device, such as electrical fuse, and the programming means can apply a high voltage to induce a high current to flow through the OTP element. When a high current flows through an OTP element by turning on a program selector, the OTP element can be programmed, e.g., burned into a high or low resistance state (depending on either fuse or anti-fuse). A programmable resistive device can also be Phase-Change RAM (PCRAM) or Resistive RAM (RRAM) that can be programmed reversely and repeatedly. Another type of programmable resistive device such as Magnetic RAM (MRAM) or Conductive-Bridge RAM (CBRAM) that can be programmed based on directions of current flowing through the resistive device.
An electrical fuse is a common OTP which is a programmable resistive device that can be programmed only once. An electrical fuse can be constructed from a segment of interconnect, such as polysilicon, silicided polysilicon, silicide, metal, metal alloy, or some combinations thereof. The metal can be aluminum, copper, other transition metals, or non-aluminum metal gate for CMOS. One of the most commonly used electrical fuses is a CMOS gate, fabricated in silicided polysilicon, used as interconnect. The electrical fuse can also be one or more contacts or vias instead of a segment of interconnect. A high current may blow the contact(s) or via(s) into a very high resistance state. The OTP can be an anti-fuse, where a high voltage makes the resistance lower, instead of higher. The anti-fuse can consist of one or more contacts or vias with an insulator in between. The anti-fuse can also be a CMOS gate coupled to a CMOS body with a thin gate oxide as insulator to be breakdown by a high voltage.
A conventional programmable resistive memory cell is shown in FIG. 2(b). The cell 10 consists of a resistive element 11 and an NMOS program selector 12. The resistive element 11 is coupled to the drain of the NMOS 12 at one end, and to a high voltage V+ at the other end. The gate of the NMOS 12 is coupled to a select signal (Sel), and the source is coupled to a low voltage V−. When a high voltage is applied to V+ and a low voltage to V−, the resistive device 10 can be programmed by raising the select signal (Sel) to turn on the NMOS 12. One common resistive element is a silicided polysilicon, which can be fabricated at the same time as a MOS gate. The size of the NMOS 12, as program selector, needs to be large enough to deliver the required program current for a few microseconds. The program current for a silicided polysilicon is normally between a few milliamps (mA) for a fuse with width of 40 nm to about 100 mA for a fuse with width about 0.6 um. As a result, the cell size of an electrical fuse using silicided polysilicon tends to be very large. The programmable resistive memory cell 10 can be organized as a two-dimensional array with all V+'s in the same columns coupled together as bitlines (BLs) and all Sel's in the same rows coupled together as wordlines (WLs).
Another programmable resistive memory cell 15 is shown in FIG. 2(c). The programmable resistive memory cell has a programmable resistive element 16 and a diode 17 as program selector. The programmable resistive element 16 is coupled between an anode of the diode 17 and a high voltage V+. A cathode of the diode 17 is coupled to a low voltage V−. By applying a proper voltage between V+ and V− for a proper duration of time, the programmable resistive element 16 can be programmed into high or low resistance states, depending on voltage/current and duration. The diode 17 can be a junction diode constructed from a P+ active region on N well and an N+ active region on the same N well as the P and N terminals of a diode, respectively. In another embodiment, the diode 17 can be a diode constructed from a polysilicon structure with two ends implanted by P+ and N+, respectively. The P or N terminal of either junction diode or polysilicon diode can be implanted by the same source or drain implant in CMOS devices. Either the junction diode or polysilicon diode can be built in standard CMOS processes without any additional masks or process steps. The programmable resistive memory cell 15 can be organized as a two-dimensional array with all V+'s in the same columns coupled together as bitlines (BLs) and all Sel's in the same rows coupled together as wordline bars (WLBs).
The conventional electrical fuse cell size using MOS as program selector is very large (˜50 um2), and the current is very high (˜20 mA) for memory repairs. The gate-oxide breakdown anti-fuse tends to have Soft Breakdown problem, instead of Hard Breakdown, such that the programmed anti-fuse can be healed by itself and cause severe reliability problems. Moreover, the anti-fuses are problematic to implement in-system repairs because of costs, capacity, and yield/reliability, and special requirements such as high voltages, charge pumps, or additional pins, etc. As a result, there is a need for improved approaches to repair memories in the wafer level, in the package, in the module, or even in the systems to increase yields and reduce costs of a memory chip or module after production.